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Make 5-level paging support unconditional for x86-64 (kernel.org)
3 points by ta988 on July 5, 2024 | hide | past | favorite | 2 comments


Neat! Had to do a quick search for what this does. We're going from 48-bit addressing to 57-bit addressing (256TB of addressable memory to 128PB of addressable memory).

https://en.wikipedia.org/wiki/Intel_5-level_paging

Windows 10 and 11 support this feature today.


Huh, this will affect all Nan-boxing vm's, like v8, luajit, etc. Didn't know that they even had this 5level config already. 9 bits less for additional types now. But in reality you would be fine even with the last 3 bits, as in most not-nan boxing fast vm's.




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