I can't agree with that -- POWER has slightly simpler addressing modes, in that `lwu` etc are always and only pre-increment/decrement, and doesn't have load/store multiple (the most CISCy thing in arm32) at all. And also, obviously, not predication, either per-instruction or with anything like `IT*`.
ARM64 gets a lot closer to CISC than ARM32, honestly (aside from the "everything predicated" and "double word stores"), with a larger suite of weirder instructions. Predication is also a distinct feature of ARM instructions, not a generic CISC thing.
POWER has instructions like RLIMI, DOZ, and STHBRX on the "complex" side.
The RISC/CISC distinction is not just about addressing and accessing memory (register-register vs register-memory operations). The headline operations for x86 actually were more about the compute side rather than the memory side - things like the "AAD" instruction did a lot of computing work in one bite. There were also RISC register-memory machines at the time the distinction was meaningful.
"General comment: this may sound weird, but in the long term, it might
be easier to deal with a really complicated bunch of instruction
formats, than with a complex set of addressing modes, because at least
the former is more amenable to pre-decoding into a cache of
decoded instructions that can be pipelined reasonably, whereas the pipeline
on the latter can get very tricky (examples to follow)."
So the distinction is more about how 'easy' an ISA lends itself to pipelining (critical paths, dependencies between instructions/operands & so on), than about how rich the instruction set is or how much work 1 instruction may do.
No way. Quite the opposite. ARM64 is quite similar to e.g. RISC-V in most respects other than the use of condition codes.
> POWER has instructions like RLIMI, DOZ, and STHBRX on the "complex" side.
There is nothing complex or "un-RISC" about any of those.
RLIMI is similar to Arm32 BFI or Arm64 UBFM.
DOZ is just subtract with the output zeroed if the MSB is 1. It is easily implemented with just a handful of straight-line instructions in any ISA with min/max or slt or for that matter asr i.e. in hardware with a simple combinatorial add-on to standard subtraction.
STHBRX is just a little-endian store (on big-endian POWER). Plenty of other RISC ISAs (whether big-endian or little-endian) have that.
> things like the "AAD" instruction did a lot of computing work in one bite
Less than other ISAs with a one-shot decimal add instruction (or mode e.g. 6502). Once again, it's a very simple combinatorial circuit -- no CISCy microcode or control flow needed.
> There were also RISC register-memory machines at the time the distinction was meaningful.
